I have been always interested to work at problems that have to do with scale either from a technology or a business perspective. VLSI (Very Large Scale Integrated) semiconductor circuits fit this category perfectly.

I started to work on algorithms to synthesize VLSI chips from formal specifications as researcher in Siemens AG in Munich. Automation of the design of application-specific integrated circuits (ASICs) promised to open the door for more economic hardware solutions, but in general it is a hard problem to solve even today.

By focusing on solutions with embedded processor cores we made significant progress and developed a “silicon compiler” called SMART (Synthesis of Modular Architectures with Test Support).

The toolset was used to develop smart sensors for automotive applications such as measurement of air volume in the intake of combustion engines (MAF sensors). Smart sensors combine analog logic to capture physical signals with a processor core to process these signals. Smart sensors are standard in cars of today and typically integrate with the digital communication bus that connects all electronic systems of a car.

An interesting aspect of our approach was the use of rudimentary processor architecture SIC (Simple Instruction Computer) that pre-dated the area of RISC (Reduced Instruction Set) processor.

SIC was optimized for the automatic synthesis from a specification while RISC-processors claim to fame was the heavy usage of compiler technology to optimize code written in a higher-level programming language. In both cases the simplified/reduced instruction set of the processor enabled more efficient optimizing transformations in the compiler and therefore reduced time to market/to execute a program.